Time-slot interchange circuit

ABSTRACT

A circuit and method are presented for signal processing and routing of digital voice telephony signals, using a specialized high-density integrated circuit voice processor. The voice processor performs several essential functions required for telephony processing, including echo cancellation, protocol conversion, and dynamic range compression/expansion. These functions are traditionally performed by multiple circuits or modules. By combining these capabilities in a single device, power and circuit board area requirements are reduced. The embodiment of the circuit and method disclosed herein include novel implementations of a time-slot interchange circuit and a telephony signaling circuit. Both of these circuits are designed to minimize demands on the signal processing engines incorporated within the voice processor, and account for very little of the on-chip circuitry.

PRIORITY CLAIM

The present application is a division of U.S. patent application Ser.No. 09/919,221, filed Jul. 31, 2001, now U.S. Pat. No. 7,346,048.

BACKGROUND OF THE INVENTION

1. Field of Invention

This invention relates to integrated circuits (ICs) for voicecommunications, and more particularly, to a highly integrated processorfor processing and routing voice traffic over a digital network. Theprocessor disclosed herein efficiently incorporates several signalprocessing and formatting operations traditionally using multiplediscrete devices, enabling substantial savings in space and powerconsumption.

2. Description of Related Art

Early voice communications was based on the transmission of analogsignals over comparatively short distances. However, the telephone soonbecame an indispensable part of modern life, for both personal andcommercial use. As the amount of voice traffic grew and the use of longdistance connections became greater, it became necessary to adopt afundamentally different method of transmitting voice signals. The reasonfor this is simple. A communications network in which every 2-wayconversation is allotted its own line works well enough for a smallnumber of users, separated by short distances. But if the number ofusers increases by a factor of 10, the telephone company must install 10times as much wire into the network. And, if many of these conversationsoccur between users at remote locations, the amount of wire can becomevery large. In fact, the material and labor demanded quickly becomesprohibitive.

A simple example illustrating the technique of time divisionmultiplexing (TDM) is presented in FIG. 1. In this example, fourdifferent voice signals from sources A-D are to be transmitted across asingle wire to a remote destination. In the first stage 24 of thisprocess, the voice signals are digitized by analog-to-digital (A/D)converters 10A-D. In other words, each of the continuous signals A-D isperiodically sampled and represented by a binary number denoting theapproximate voltage of the sample. In FIG. 1, the samples for waveform Aare represented by solid circles, while those for waveforms B, C and Dare represented by hollow circles, hollow squares and solid squares,respectively. The individual samples in each sequence may be denoted bythe letter associated with the source, with a subscript for the samplenumber. For example, the samples in the sequence derived from source Bwould be denoted B₀, B₁ . . . B_(n).

The resulting sample sequences 26 must contain sufficient information toreconstruct the original waveforms at the destination. According to theNyquist Theorem, this requires that each waveform be sampled at a rategreater than twice the highest frequency present in the waveform. Forexample, a signal containing frequencies of up to 1 KHz must be sampledat a rate greater than 2 KHz, to permit the signal to be reconstructedfrom its discrete samples. In the case of standard voice communications,signals are assumed to be band-limited to about 3 KHz, so a samplingrate of 8 KHz is often used. This implies that the sample interval(i.e., the time interval between any two adjacent samples) in thesequences 26 can be 125 μs.

A multiplexer 12 combines the four sample sequences 26 into amultiplexed sequence 28. Two characteristics of this multiplexedsequence are particularly noteworthy. First, the original four samplesequences are interleaved to create the multiplexed sequence. Thus, thesample order in the multiplexed sequence is:

-   -   A0, B0, C0, D0, A1, B1, C1, D1 . . . A_(n), B_(n), C_(n), D_(n)        Note that this preserves the original order of the samples.        Second, the effective sample rate in the multiplexed sequence is        four times that of the original sequences. Within each 125 μs        sample interval, the multiplexer 12 must collect a new sample        from each of the four sources and transmit all four samples.        Consequently, the samples in the multiplexed sequence 28 can be        separated by 31.25 μs, for an effective sample rate of 32 KHz.

The multiplexed sample sequence 28 is typically buffered by a high-speedamplifier, which drives the impedance of the wire, cable, transmissionline 16, etc. used to convey the sequence to the desired remotedestination. At the destination, another amplifier receives the signalfrom the transmission line 16 and conditions (filtering, glitchsuppression, etc.) it before presenting it to the input of ade-multiplexer 20. The de-multiplexer 20 reverses the operationsperformed by multiplexer 12, to extract the original four samplesequences 26 from the multiplexed sequence 28. Each of the resultingsample sequences may then be acted upon by a digital-to-analog (D/A)converter 22A-D to reconstruct the respective voice signals 30.

In the preceding example, only four signals were multiplexed. However,the TDM principle can clearly be extended to transmit greater numbers ofvoice signals over a single line. In fact, the upper limit on the numberof voice channels that can be carried is related to the amount ofavailable bandwidth, commonly stated in terms of the maximum bits persecond (bps) sustainable by the hardware. Along with the number ofsignal sources (or, channels) and the sample rate, the bandwidthrequired for a TDM transmission depends on the number of bits persample. For voice communications, signals are usually digitized to 8bits. Thus, the bandwidth required can be expressed as: bandwidth(bps)=no. of channels×no. of bits per sample×sample rate. The originalT-carrier system developed in the 1970's allows for 24 voice channels tobe multiplexed onto a single line, using the techniques described above.If each channel is sampled with 8-bit resolution at a rate of 8 KHz, theTDM bandwidth required is: 24×8×8000=1.536 Mbps. The original T1standard defines a data structure known as a D4 frame for the transportof TDM data. A D4 frame consists of 24 consecutive 8-bit samples (onefrom each voice channel), preceded by a framing bit. Note that theaddition of the framing bit alters the previous TDM bandwidthcalculation. Since each frame consists of 24×8+1=193 bits, and framesare transmitted at 8000 frames per second, the bandwidth becomes:(24×8+1)×8000=1.544 Mbps. The framing bit follows a special patterncalled the frame alignment signal, which repeats every 12 frames. Thegroup of 12 consecutive frames bounded by this frame alignment signal isknown as a superframe.

T1 performance is easily achieved with today's technology, and thedemand for greater bandwidth soon led to the introduction of otherstandards, embodied in the following digital signal hierarchy (DSH):

DS Level North American Bandwidth Voice Channels T-Carrier DS0 64 Kbps 1DS1 1,544 Mbps 24 T1 DS2 6,312 Mbps 96 DS3 44,736 Mbps 672 T-3Thus, for example, a single T-3 line supports 672 DSO voice channels.

Since data in a frame is multiplexed, it is possible to reroute data byrearranging the time slots between incoming and outgoing channels. Thisis accomplished by a device known as a time-slot interchanger (TSI).FIG. 2 illustrates the operation of a TSI. As described above, amultiplexer 100 collects one sample from each of 24 incoming voicechannels, at a sample rate of 8 KHz. These samples are placed in amemory buffer 102; their location in the buffer is based on the channelfrom which they originated. The TSI 104 rearranges the order of thesamples and places the re-ordered samples in an outgoing buffer 106(while another incoming frame is being entered into the first buffer102). A de-multiplexer 108 then scans the outgoing buffer and assignsthe samples to voice channels in a different sequence. A significantamount of memory is required for the TSI to re-sequence the time slots.If two entire frames of data must be buffered, a total of 384 bits ofmemory is needed. Furthermore, complex support circuitry is necessary tocontrol the flow of data. Since both the memory and ancillary circuitrymust operate at relatively high speeds, TSI modules can be costly,especially as channel capacities increase beyond T1 rates through theTSI.

In addition to voice data, line status information may be sent over atelephone connection. Voice band signaling is a method of placing linestatus bits within the voice data. In the simple case, two bits areincluded in a sixth frame of a D4 superframe on a T1 connection toindicate the on-hook/off-hook status of a call. The so-called A-bit andB-bit used for this purpose are inserted in the least significant bit ofeach of the 24 time slots in the 6^(th) and 12^(th) frames,respectively, of the superframe. Since the signaling bits overwritevoice data, this technique is referred to as “robbed bit” signaling. Anextended superframe (ESF), consisting of 24 D4 frames, allows theaddition of a C-bit (in the 18^(th) frame) and D-bit (in the 24^(th)frame). Alternatively, the line status information can be sent on aseparate connection, by a technique known as “clear channel” signaling.

As described above, voice signals are typically encoded using timedivision multiplexing (TDM) for transmission over the telephone network.However, there is an undesirable characteristic of TDM, whichpotentially reduces its efficiency. Under TDM, the mapping of time slotsto voice channels within a frame is fixed. Consequently, a time slotallotted for a particular voice channel may go unused, if the signalsource for that channel is inactive during its time slot. This typicallyoccurs with “bursty” signals, which consist of active signal intervalsseparated by periods of inactivity. Significantly, normal speech is abursty signal. With such signals, the frame may be transmitted with lessthan its full capacity, since many of its timeslots may contain samplescollected during a period of inactivity. An approach that overcomes thislimitation is asynchronous transfer mode (ATM). Asynchronous transfermode (ATM) is a switching technology that can organize digital data into53-byte cells for transmission over a physical medium. Each cell mayconsist of one 5-byte header and a 48-byte payload, containing theactual data to be transmitted. Individually, a cell is processedasynchronously relative to other related cells and is queued beforebeing multiplexed over the transmission path. ATM presents the cells(containing the voice samples) to the network whenever there is enoughbandwidth available to handle them. In this sense, the voice datatransfer is asynchronous relative to the generation of the originalvoice signal. In addition to voice, ATM supports various other types ofsignals and data, including video and multimedia applications. In an ATMnetwork, data must be divided into cells before transmission andreconstituted from cells upon reception. This is known as segmentationand reassembly (SAR), and is typically handled by a hardware device(i.e., electronic circuitry).

A T1 connection can directly route frames from a source to designateddestination. In contrast, ATM allows flexibility in the choice of aconnection path. The 5-byte header within each 53-byte ATM cell containsa virtual path identifier (VPI) and virtual channel identifier (VCI).The VPI and VCI are used to route the cell to its intended destination.This allows the ATM switching hardware to efficiently allocateconnection paths based on the level of activity in the voice channels.Because the cells are always the same size, dedicated hardware designsfor high-performance ATM switches are relatively straightforward. As aresult, ATM networks can operate at speeds greater than 155 Mbps.

Voice data formatted as ATM cells can be transmitted over a T1connection by using a network adaptor. The network adaptor converts the53-byte ATM cells into a sequence of samples, which are assigned to thetimeslots within three frames (since each frame contains 24 bytes ofdata, the 53 cells must be spread over three frames). This process canalso be reversed to generate ATM cells from T1 frames. The conversionbetween ATM and T1 data formats can be employed to efficiently routevoice traffic through the telephone network.

Within the telephone system network, a central office (CO) is an officelocal to a group of subscribers (i.e., telephone system users). Home andbusiness lines are connected to a CO by what is called a local loop. Thelocal loop connection is usually on a pair of copper wires calledtwisted pair. The voice signals from each subscriber are typically inanalog form (i.e., continuous) over the local loop, but are transformedinto digital data at the CO. The CO also has switching equipment thatcan switch calls locally or to long-distance carrier phone offices. Theconversion from T1 to ATM is useful for combining a large number ofvoice channels to be transmitted over a long distance by ahigh-bandwidth link (such as optical fiber) connecting one centraloffice to another within the telephone network.

Normal voice communications is connection-oriented. That is, aconnection between the talker and the listener must be establishedbefore voice data is transmitted. In contrast, data communicationnetworks, such as the Internet, or a local area network (LAN) in anoffice, are inherently connectionless. The model for such networks isthat of a single communications line, shared by several nodes.Connectionless network service does not predetermine the path from thesource to the destination system. Messages are sent out on the sharedline in the form of packets (also known as datagrams). Each packet isdirected to a particular node through the inclusion of the recipient'saddress in header information associated with the message. Packets mustbe completely addressed because different paths through the networkmight be selected (by routers) for different packets, based on a varietyof influences. Each packet is transmitted independently by the sourcesystem and is handled independently by intermediate network devices. Theconnectionless mode of operation is more appropriate for many types ofdata communication. For example, when sending an email message out overthe Internet, it would be inconvenient to require the intended recipientof the email to have previously established a connection channel throughwhich to receive the email.

Voice data may be formatted to allow transmission over a connectionlessnetwork by segmenting the data into appropriate-sized frames, prefixedwith the required header information. This conversion is termed dataencapsulation. Data encapsulation could be necessary, for example, atthe interface between the public switched telephone network (PSTN) andan optical fiber-based LAN. The Transmission Control Protocol/InternetProtocol (TCP/IP) suite, described below, may be used for theencapsulation and delivery of voice data over a connectionless network.The function of the various protocols in the TCP/IP suite may beunderstood with reference to the following open systems interconnect(OSI) 7-layer model.

(2) (7) (6) (5) (4) (3) DATA (1) APPLICATION PRESENTATION SESSIONTRANSPORT NETWORK LINK PHYSICAL LAYER LAYER LAYER LAYER LAYER LAYERLAYER Email HTTP POP3 TCP IP Ethernet ADSL File Transfer FTP IMAP UDPATM SLIP coaxial cable Web Applications Telnet MAC RTP

In the OSI model, the process of communication between two computersconnected by a telecommunication network is divided into layers. When amessage is transmitted from one computer to the other it passes downthrough the various layers on the sender's side of the network, and backup through the protocol layers when it is received at the receiver'sside.

-   -   (1) The Physical Layer is the lowest level of the OSI model, and        the protocols here define actual physical medium for the        transport of a bit stream from one point in the network to        another.    -   (2) The Data-Link Layer defines the access strategy for the        physical medium, and pertains to hardware devices such as        network interface cards (NICs), routers and bridges.    -   (3) The Network Layer governs the routing and forwarding of data        through the network.    -   (4) The Transport Layer provides error-checking and ensures that        all the data sent have been received at the destination.    -   (5) The Session Layer coordinates exchanges between two        computers over the network to ensure that the connection is        preserved until the transaction is completed.    -   (6) The Presentation Layer, usually part of an operating system,        is the point at which data sent is rendered into a format usable        by the recipient—e.g., transformation of a byte stream into a        displayable image.    -   (7) The Application Layer is the layer at which network-oriented        applications programs reside—these applications are the ultimate        target of the message transmitted by the sender.

The IP is a Layer 3 protocol, most familiar as the protocol by whichdata is sent from one computer to another on the Internet. Each computer(known as a host) on the Internet has at least one IP address thatuniquely identifies it from all other computers on the Internet. Whendata is sent or received (for example, an e-mail note or a Web page),the message gets divided into packets, each of which contains both thesender's and the receiver's Internet address. Packets are first sent toa gateway computer that directly accesses a small neighborhood ofInternet addresses. If the destination address is not directlyaccessible to the gateway computer, it forwards the packet to anadjacent gateway. This process continues until one gateway recognizesthe packet as belonging to a computer within its immediate neighborhoodor domain. That gateway then delivers the packet directly to thecomputer whose Internet address is specified.

IP is a connectionless protocol, which means that there is no continuingconnection between the end points that are communicating. Each packetthat travels through the Internet is treated as an independent unit ofdata without any relation to any other unit of data. Consequently, thepackets comprising a message may take different routes across theInternet. Furthermore, packets can arrive in a different order than thatin which they were sent. The IP accounts for their delivery to thecorrect recipient, but does not manage the delivery sequence. In thecontext of the Internet, the Layer 4 Transmission Control Protocol (TCP)is generally relied upon to arrange the packets in the right order, andthe two protocols are often jointly referred to as TCP/IP. Analternative to TCP (also at Layer 4) is the User Datagram Protocol(UDP), which offers a limited amount of service when messages areexchanged between computers in an IP-based network. Like TCP, UDP usesthe IP to actually get a packet from one computer to another. UnlikeTCP, however, UDP does not provide the service of dividing a messageinto packets and reassembling it at the other end. However, UDP doesprovide port numbers to help distinguish different user requests and,optionally, checksum capability to verify that the data arrived intact.UDP is used by applications that do not require the level of service ofTCP or that wish to use communications services not available from TCP

Realtime transport protocol (RTP) is an IP-based protocol providingsupport for the transport of real-time data such as video and audiostreams. A Layer 4 protocol, RTP provides time-stamping, sequencenumbering and other mechanisms related to managing timing issues in suchdata. The sender creates a timestamp when the first voice signal samplein a packet is collected, and this timestamp is then attached to thedata packet before sending it out. The receiver may use this informationto assemble the packets in their correct sequence, or to synchronize onepacketized data stream with another—for example, in the case oftransmitted audio and video data from a movie. RTP also provides otherservices, such as source identification. Using the source identifier inthe RTP header of an audio packet exchanged during a video conference,for example, a user can identify who is speaking.

Information required by each protocol is contained in a header attachedto a data packet as it makes its way through the network. Headerinformation associated with the protocols at different OSI layers can benested. For example, data sent from an application may begin as an RTPpacket:

As the packet moves down through the OSI layers to be transmitted overthe physical medium, a UDP header is prepended, followed by an IPheader:

It is often necessary to transform voice from the connection-orientedframe-based TDM format used by the PSTN to a connectionless cell-basedformat, such as that used by ATM, or a packetized format such as used byan Ethernet network. A significant effort in such transformations isdevoted to the preparation and attachment of header information to thedata.

In addition to the various formatting operations described above, whichare required to prepare voice data for transmission over the telephonesystem or a network, there is considerable signal processing involved invoice communications.

To reduce the amount of bandwidth required for their transmission overthe telephone network, the dynamic range of voice signals is generallyreduced, using one of various standard compression algorithms. At thereceiving end, the original dynamic range of the signal is restored by acomplementary expansion algorithm. The dynamic range of an audio signalis the difference between the loudest part of the signal and thequietest part. When an analog signal is translated into digital samples(a process known as quantizing, or digitizing the analog signal), thecontinuous range of values comprising the signal are approximated by afinite set of discrete values. The resolution of the sampling processrefers to the number of discrete values used in this approximation, andthe discrete value closest to the actual value of the analog signal isalways used to approximate the signal. For example, assume that ananalog signal always has a value V_(S) within the range of 0.0-4.0Volts, and that 4 equally-spaced discrete values (0.5, 1.5, 2.5 and 3.5)are used to represent the signal. The following chart illustrates howthe closely the discrete values approximate the analog signal:

DISCRETE VALUE ACTUAL ANALOG VOLTAGE APPROXIMATION   0 ≦ V_(s) < 1.0Volts 0.5 Volts 1.0 ≦ V_(s) < 2.0 Volts 1.5 Volts 2.0 ≦ V_(s) < 3.0Volts 2.5 Volts 3.0 ≦ V_(s) < 4.0 Volts 3.5 Volts

The worst-case error with this approximation is ±0.5 Volts, which isequivalent to 12.5% of the full dynamic range of the signal. However, ifthe same dynamic range is divided into a larger number of discretevalues, the accuracy of the approximation can be greatly improved. Forexample, the following chart illustrates the improvement in worst-caseerror if 256 discrete values are used instead of 4:

DISCRETE VALUE ACTUAL ANALOG VOLTAGE APPROXIMATION 0 ≦ V_(s) < 0.015625Volts  0.078125 Volts 0.015625 ≦ V_(s) < 0.03125 Volts 0.0234375 Volts .. . . . . 3.984375 ≦ V_(s) < 4.0 Volts 3.9921875 Volts

In this case, the worst-case error becomes ±0.015625 Volts. Thus, usinga large number of distinct values results in a more accurateapproximation. However, it also requires that more bits be used torepresent each sample. By reducing the dynamic range, fewer bits can beused to obtain a given worst-case error. Uncompressed audio requires16-bit resolution. At a sampling rate of 8 KHz this results in arequired bandwidth of 128 Kbps. By compressing the dynamic range so that8-bit samples can be used, the bandwidth requirement is only 64 Kbps.

Dynamic range compression results in a loss of information. That is tosay, a signal that has been compressed and restored will not exactlymatch the original signal. However, the standard compression algorithmsfor voice communications are designed so that these losses are notnoticeable. Two of the more widely used compression techniques are theμ-law and adaptive differential pulse code modulation (ADPCM)compression algorithms. μ-law compression is based on sampling alogarithm of the analog signal, rather than the signal itself. Thelogarithm has a narrower range of values than the raw signal. Forexample, if the voltage of the uncompressed voice signal has a maximumvalue of 10.0, its base-10 logarithm has a maximum value of only 1.0.Routines exist for highly efficient calculation of logarithms by digitallogic (e.g., a computer or dedicated signal processor). Advantageously,the original signal can be recovered from the logarithm by computing thecomplementary antilogarithm.

ADPCM is an enhanced form of differential pulse code modulation (DPCM).Instead of quantizing the signal itself, DPCM quantizes the differencebetween successive samples of the signal—hence the use of the term“differential”. ADPCM, is an adaptive version of this technique, inwhich the assumptions based on the previous quantized sample are used torestrict the presumed range of values for the next sample. Thisalgorithm uses only 4 bits to represent each sample of a voice signal.

In addition to compression, voice signals over the telephone network mayalso require echo cancellation. Echoes result from the reflection ofelectrical signals (usually arising from mismatched impedances) back tothe sender from the receiving end of the line. The severity of the echois related to the transit time for the signal to travel from the senderto the receiver, which in turn depends on the electrical path lengthbetween sender and receiver. If the distance is short, the echo returnsso quickly that it is not perceptible. On the other hand, if the pathlength is sufficient to create a delay in the echo on the order of 10 msor more, the effect can be disruptive to normal telephone conversations.In fact, the “threshold of annoyance” for echo is also related to theloudness of the echo in relation to the primary voice signal.Consequently, even if echo cannot be completely eliminated, by reducingits amplitude sufficiently it can be rendered unobtrusive.

Echo canceling algorithms are typically implemented using a digitalsignal processor (DSP), which is a high-speed microprocessor speciallyadapted for numeric computation. Such algorithms are typicallyadaptive—that is, they are able to quickly “learn” the transmit/receivecharacteristics of the line during the first few seconds after aconnection is made, and also respond to any changes in thosecharacteristics while the line is active. Over the course of aconversation, the DSP monitors the digitized voice signals beingtransmitted and predicts the corresponding echo signal. The predictedecho is simply subtracted from the actual return signal.

The various switching, formatting and signal processing operationsperformed on voice data have necessitated the use of extensiveelectronic circuitry in the central offices and other nodes within thetelephone network. Furthermore, because of their specialized nature,these operations are generally handled independently by discreterack-mount circuit cards and modules. Unfortunately, this has led to aproliferation of electronic devices to deal with large numbers ofincoming and outgoing lines. The consumption of power and spaceattributable to these devices is a serious problem. Excessive heatgeneration and its impact on system reliability, are a further concern.

In view of these problems, it would be desirable to have a single deviceintegrating many of the functions described above. The device shouldsupport compression and echo canceling signal processing functions. Itshould also be capable of segmenting data and providing headers to allowtranslation of frame-based and/or cell-based data formats, such as RTPpackets or ATM cells. In addition, the device should be able to performtime slot interchange on incoming and outgoing TDM data, and shouldallow detection of both voice band and clear channel signaling.Furthermore, the device power consumption should be low, to mitigateheat dissipation problems associated with multi-device installations.

SUMMARY OF THE INVENTION

The problems outlined above are addressed by a specialized high-densityintegrated circuit for signal processing and routing of digital voicetelephony signals. In addition to standard signal processing functions,such as dynamic range compression/expansion and echo canceling, theimproved voice processor supports the conversion between cell-based orpacket-based data and traditional frame-based telephony data. The voiceprocessor also employs an efficient DMA-based protocol stack andindependent processor for the creation and management of cell or packetheaders, as well as an independent CRC/Checksum engine. Thus, protocolprocessing and error detection have minimal impact on concurrent signalprocessing operations.

A time-slot interchange circuit within the voice processor is provided.In an embodiment, this TSI employs a small memory buffer with a storagelocation for each of multiple data streams. Short bit sequences fromincoming time division multiplexed (TDM) data streams may be stored inthese locations before they are placed into outgoing streams. Time slotinterchange is accomplished by switching circuitry, which redirects bitsoccupying a given TDM time slot in an incoming data stream to anoutgoing stream other than the one corresponding to the input stream.This effectively replaces the bit sequence originally occupying the timeslot in the ‘target’ data stream. Advantageously, this technique doesnot require buffering entire incoming and outgoing frames.

A TSI method is also disclosed, for rearranging time slots in TDM framesarriving as multiple input data streams before transmitting the data asoutput data streams. The method calls for using a memory buffer to storea short incoming bit sequence from an incoming data stream, and thenplacing the bit sequence in the same relative position (i.e., time slot)in any output data stream or streams.

A telephony signaling circuit is within the voice processor disclosedherein. Using the telephony signaling circuit, the processor is able torespond to changes in line status indicated by signal bits. Theprocessor can also effect changes in line status by altering the signalbits. The telephony signaling circuit contains a comparison register foreach of the incoming TDM lines, in which the current and previous signalbits are stored. For each comparison register, there is an associateddata comparator that compares the signal bits previously stored in thecomparison register against the current signal bits. If the previoussignal bits differ from the current signal bits, the signal bits storedin the comparison register are replaced with the new signal bits, andthe associated digital signal processor (DSP) is interrupted, allowingit to respond to the change in line status.

The telephony signaling circuit also contains a modification registerand a data modifier for each of the outgoing TDM lines. The modificationregister stores signal bits received from the DSP. When commanded by theDSP, the data modifier places the signal bits stored within themodification register over the respective outgoing TDM line. The alteredsignal bits are interpreted by other telephony equipment as a change inthe line status. An alternate mode of operation is available in whichthe packet control processor (PCP) is notified of changes in the linestatus, rather than the individual DSPs. In this mode, it is also thePCP that alters the line status.

A method for telephony signaling is also provided, according to whichcurrent signal bits on incoming TDM lines are stored, along with theprevious values of those bits. When a comparison between the current andprevious signal bit values indicates that they have changed, a DSP isnotified. In addition, the method calls for the DSP placing signal bitsand a channel designator in a modification register, and a data modifierusing this information to alter the signal bits for the designatedoutgoing TDM line.

In an embodiment of the voice processor disclosed herein, severalessential capabilities for telephony processing are combined in a singledevice. As compared to conventional solutions, demanding multiplediscrete devices, power and circuit board area requirements are reduced.Both the time-slot interchange circuit and telephony signaling circuitare designed to operate independently of the signal processing engineswithin the voice processor and to occupy very little additional space onthe semiconductor substrate.

BRIEF DESCRIPTION OF THE DRAWINGS

Other objects and advantages of the invention will become apparent uponreading the following detailed description and upon reference to theaccompanying drawings in which:

FIG. 1 illustrates the use of time division multiplexing (TDM) totransmit multiple voice channels using a single line;

FIG. 2 illustrates the operation of a conventional time slot interchange(TSI) circuit;

FIG. 3 contains a block diagram of an embodiment of a voice processor;

FIG. 4 illustrates the operation of the time slot interchange (TSI)circuit employed in an embodiment of the voice processor; and.

FIG. 5 illustrates operation of the telephony signaling circuit employedin an embodiment of the voice processor.

While the invention is susceptible to various modifications andalternative forms, specific embodiments thereof are shown by way ofexample in the drawings and will herein be described in detail. Itshould be understood, however, that the drawings and detaileddescription thereto are not intended to limit the invention to theparticular form disclosed, but on the contrary, the intention is tocover all modifications, equivalents and alternatives falling within thespirit and scope of the present invention as defined by the appendedclaims.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Telephone voice signals originate in analog form, but travel relativelyshort distances before being converted to digital format, fortransmission across high-bandwidth networks. To maximize the use oftransmission media, such as wire, coaxial cable and fiber optic,multiple digitized voice signals are time division multiplexed (TDM)onto a single line. Throughout the telephone network, gateway sitesmanage this communications activity, providing signal processing,switching, protocol translation, etc. Given the high volume of voicedata traffic, a great deal of circuitry is required to perform theseoperations. Therefore, the power efficiency and space utilization of theassociated circuitry are highly important issues.

A design for a highly-integrated voice processor is presented. The voiceprocessor combines diverse functionality traditionally requiringmultiple devices or modules. Furthermore, the voice processor employsnovel implementations of some of these functions, allowing its circuitryto be simplified. As a result, the size and power consumption of thevoice processor are significantly reduced, relative to conventionaldiscrete approaches. For example, the present embodiment of the voiceprocessor is estimated to consume roughly 15 mW of power per activevoice channel. In contrast, an implementation of the voice processorfeature set based on general purpose DSPs and supporting circuitry wouldconsume at least 35 mW per active channel. The following discussionpresents an overview of the basic architecture and major functionalcomponents of the voice processor. A detailed description is thenprovided of some of its novel features and modes of operation.

FIG. 3 contains a block diagram of an embodiment of the voice processor.The major components and signal paths within the processor are shown inFIG. 3, all of which can be present on a single monolithic semiconductorsubstrate. Signals to/from the outside (i.e., outside the processor) arerepresented as broad arrows. The processor has two major signalinput/output paths. The first is a set of 8 bi-directional serial dataconnections 84, over which frame-based data is exchanged between theprocessor and a TDM port, such as a T1 backplane. The second is theATMSAR port 80, over which packetized or cell-based data is exchangedbetween the processor and a connectionless network, such as Ethernet. Inaddition, a host processor interface (HPI) 58 allows control of thevoice processor's internal functions by an external host processorconnected to host processor bus 76, and an external memory interface 82allows the use of supplemental off-chip memory.

In the present embodiment, the voice processor contains four digitalsignal processors (DSPs), 60A-D, which operate independently of oneanother. Based on the popular “Harvard” architecture, each of theseprocessors has its own 64K×16-bit program instruction memory space(62A-D) and 48K×16-bit data memory space (64A-D). The voice processorcontains 8 external serial ports 84 through which it can receive andtransmit TDM-format data (e.g., from a framer). The serial ports arebi-directional and (in each direction) comprise three signals—data, syncand clock. Data to/from the external serial ports passes through a timeslot interchange (TSI) circuit 74. Each of the DSPs 60A-D are providedwith a pair of internal serial ports 70A-D and 72A-D, through which theDSPs interface to the TSI 74. Serial port associations for incoming andoutgoing TDM data can be dynamically reassigned by the TSI circuit 74(as discussed in detail below). The voice processor supports both voiceband and clear channel telephony signaling, through the provision of atelephony signaling circuit 68A-D (discussed in detail below) coupled toone of the two serial ports 72A-D associated with each of the DSPs. Thedata memory 64A-D associated with the DSPs 60A-D is accessible by boththe DSP and the associated dynamic memory access (DMA) controller 66A-D,and can service two or more read or write requests simultaneously. Toaccomplish this, each of the data memories 64A-64D is segmented. Asegmented memory space is subdivided into quasi-independent sections. Aslong as simultaneous memory accesses are not made to the same segment(referred to as a collision), the memory can be shared withoutperformance degradation due to contention. This capability is exploitedin the voice processor to enhance data throughput. For example, bothinternal serial ports 70A-D and 72A-D associated with each DSP 60A-D usethe respective DMA controller 66A-D to directly access the data memoryof the DSP. This is much faster than if it were necessary to invoke theDSP itself to move data between the serial port and memory. Specialcircuitry within the serial ports applies μ-law dynamic rangecompression and expansion on incoming and outgoing voice data, avoidingthe need for the DSP to expend processor cycles performing thisoperation.

A packet control processor (PCP) 45 is also included in the presentembodiment of the voice processor. This device is a general purposemicroprocessor with a reduced instruction set computer (RISC)architecture, and can be based on the ARM922 microprocessor. Supportingthe PCP 45, can be a 32K×32-bit buffer memory 48, a 4-port memoryarbiter 52 and a (cyclic redundancy check) CRC checksum engine 46. ThePCP also has its own 2K×32-bit instruction memory 54 and 2K×32-bit datamemory 56. An ARM peripheral bus (APB) controller 44 interfaces the PCP45 to low-speed peripheral devices, such as a set of 8 16-bit timers 40and a universal asynchronous receiver and transmitter (UART) 42. TheUART 42 allows an external terminal or computer to interact with the PCPover serial bus 78, and would typically be used for debugging or codedevelopment. The PCP 45 serves a number of functions in the voiceprocessor. One of the principal responsibilities of the PCP is themanagement of a protocol stack for packetized data. As describedearlier, data packets contain a header compounded from informationassociated with the protocols at different OSI layers. When datareceived through the external serial ports 84 is prepared fortransmission out of ATMSAR port 80 onto a network, the data must bereorganized as packets or cells, and the appropriate header attached toeach packet or cell. The PCP 45 builds this header, according to theselected output data format, and prefixes it to outgoing packets orcells. This process is reversed when packetized data received intoATMSAR port 80 is transmitted in frame-based format to a TDM port, usingexternal serial ports 84. The PCP 45 then strips the headers from theincoming data and reorganizes the data as frames, before transmitting itout the external serial ports 84. ATMSAR 50 may be configured to eitherdirectly send/receive packetized data over ATMSAR port 80, or firstsubdivide/reconstruct the data into/from ATM cells.

The PCP also coordinates the operation of the DMA controllers 66A-D and4-port memory arbiter 52 to manage the transfer of data between the DSPsand the ATMSAR. Incoming data is thus properly allotted to the DSPsegmented data memory 64A-D, allowing the processing of this data to beshared among the DSPs 60A-D, thereby optimizing data throughput.Furthermore, the PCP performs error detection and overall managementfunctions in the absence of an external host processor.

As discussed previously, a time slot interchange (TSI) circuit reroutesdata by rearranging the time slots between incoming and outgoingchannels. In the general case, a minimum of 256 bytes of memory isrequired to buffer both the incoming frame and the outgoing frame (withthe modified channel assignments). A novel TSI design is adopted in thevoice processor, which obviates the need for such large buffers. Invoice processing applications for which the voice processor is intended,incoming TDM data is typically received from a framer or similar device.This implies that the data streams will already have been synchronizedto a common clock rate, eliminating the need for the TSI in the voiceprocessor to buffer and synchronize an entire incoming frame of databefore rearranging the time slots.

FIG. 4 illustrates the operation of an embodiment of the simplified TSIemployed in the voice processor. In FIG. 4, each of the 8 voiceprocessor serial ports (items 70A-D and 72A-D in FIG. 3) receives a TDMdata stream 120 a-h, consisting of 192 bits of serial data at a rate of1.544 Mbps. The bit stream on each of the 8 input ports represents asequence of 8-bit voice data samples, each of which corresponds to atime slot. Thus, for example, bits A1-A8 represent the first time slotin the TDM data stream 120 a into port 1, while bits B8-B16 representthe second time slot in the TDM stream 120 b into port 2. Eight 2-bitbuffers 124 a-h (one for each of the serial ports 70A-D and 72A-D shownin FIG. 3) are used to interchange the time slots, representing a totalof only 16 bits of storage. Each buffer functions like a shift register.Synchronous with each data clock, an incoming bit 122 a-h from thecorresponding incoming TDM data stream is placed in the first locationof the buffer, while the bit previously held in the first location isshifted into the second location. Eight 8-input multiplexers 130 a-hreassign incoming data bits to outgoing data streams. Each multiplexeris associated with one of the outgoing TDM lines 132 a-h, and is capableof taking a data bit from the buffer corresponding to a given incomingdata stream and placing it in its associated output data stream. Forexample, Mux B 130 b may select a bit from buffer 124 h and place itinto outgoing data stream 132 b. As the 2-bit buffers advance the datafrom the first to the second location, the bit selected by eachmultiplexer is clocked into the respective outgoing data stream. Forexample, as the n+1^(th) bit in the data stream incoming through port 2,B_(n+1) 122 b, is clocked into the first stage of buffer 124 b, bitB_(n) moves from the first stage to the second stage of the buffer. Atthe same time, bit B_(n−1) is clocked into one of the outgoing datastreams 132 a-h, depending on which of the multiplexers MuxA 130 a-Mux H130 h has selected buffer 124 b.

Time slots are interchanged by using the multiplexers as described aboveto transpose all 8 bits of an incoming sample (i.e., a time slot) to aprescribed outgoing data stream. In the example shown in FIG. 4, bitsarriving in the data stream received at port 2 are placed in the datastream sent out over port 1. As a result of this reassignment, over thecourse of 8 consecutive 125 ns intervals an entire sample received atthe input of port 2 will appear at the output of port 1, while thesample received at the input of port 8 will appear at the output of port2, etc.

The movement of incoming data from the serial ports into the buffer mustbe fast enough to keep up with the incoming data rate. Advantageously,the TSI circuit and method disclosed herein are suitable for operationat very high speeds. The present embodiment of the TSI will support datarates on the TDM ports of 128 channels at 8 Mbps.

Note that simplified examples have been used to illustrate the operationof the TSI circuitry apart from other components of the voice processor.In practice, incoming TDM voice data is not simply rerouted, buttypically undergoes processing in the DSPs 60A-D. In this case, the TSImay be used to reassign time slots to different DSPs. This may be doneto dynamically balance the workload of the DSPs. It was stated abovethat the simplification of the TSI is founded on the assumption thatdata arriving at all 8 serial ports is synchronous. However, atransparent mode of operation is also available in the TSI to supportindependently clocked data streams. In transparent mode, the clock dataand sync line of each external serial port is directly connected to thecorresponding lines of the internal serial ports. This is in contrastwith the normal synchronous mode, in which the clock and sync signals ofserial port 0 provide the timing for all 8 ports.

The transfer of frame-based data into or out of the DSP data memory isfacilitated by the use of indexed DMA controllers, which targetprescribed regions within the DSP data memory. As mentioned above, theDSP data memory supports multi-port access, so reads and writes canoccur to two non-overlapping segments simultaneously. Collisions areavoided through the use of a linked list of buffer managementdescriptors (BMDs). Each BMD is a data structure containing the locationand size of a buffer region, a flag indicating whether the region isvacant, and a pointer to the next BMD in the list. Since the last BMD inthe list points to the first, the DMA buffer regions are organized as aring. The indexed DMA controller contains a pointer to the nextavailable BMD (i.e., the next BMD in the ring whose buffer region doesnot contain valid data). Also included within the BMD are CRC andchecksum values, used for error checking. The size, number, etc. of theBMDs and their corresponding buffer regions are defined by the PCP.

When incoming frame-based data is received (over serial ports 70A-D and72A-D in FIG. 3), each channel is assigned a DSP and a BMD pointermapping the data to a particular buffer region in the DSP data memory(items 64A-D in FIG. 3). When data is placed into a buffer area, theflag in the corresponding BMD is set to indicate that the buffercontains valid data. Signal processing operations, such as echocanceling, are then performed by the DSP on each channel of data withinthe respective buffer regions. If the processed data is to be outputonto a network, it must be appropriately formatted. This requires thedata to be organized as packets or ATM cells, with headers correspondingto the network protocol stack. Much of this functionality is implementedin the PCP (item 45 in FIG. 3).

In the present embodiment of the voice processor, the PCP is a 200 MHz32-bit RISC-type processor, which has DMA access to the data memory ofeach DSP. To prepare processed data for export on a network, the data isfirst transferred from the DSP memory to the 32K×32-bit buffer memory(item 48 in FIG. 3). Note that since this is a DMA transfer from amulti-port memory, DSP execution is not impeded. Within the PCP buffermemory, the data is reorganized as variable length packets and asequence of encapsulation steps carried out, in which headers for thevarious levels of the operative protocol stack are added to each packet.Thus, a complete packet consists of a header portion and the transmitteddata itself (often referred to as the “payload”). As the compositeheader is constructed, the CRC/Checksum engine (item 46 in FIG. 3)computes cyclic redundancy and checksum values, which will be used toverify the integrity of the transmitted data.

For example, packets may be prepared for transmission over a SynchronousOptical NETwork (SONET). The SONET standard for digital opticaltransmission was introduced in the late 1980's to provide a means fordigitally encoding voice, video and other information for transmissionover optical fiber. In this case, the interface to the network overwhich the data may be transmitted is a “packet over a SONET-PhysicalLayer Interface” (POSPHY), and the data packets require a compositeheader containing RTP/UDP/IP protocol layers.

In the present embodiment of the voice processor, the composite packetheader is constructed in a highly efficient manner through the use offixed header templates. Rather than compute entire packet headers “fromscratch,” a header template is prepared in advance for each active datachannel, based on the particular protocol stack, and placed in aprescribed location within the 32K×32-bit PCP buffer memory.Conveniently, the basic structure of the header will not change from onepacket to another, and only certain fields (e.g., packet length,checksum, etc.) within the header will need to be modified. Thesevariable fields are updated by the PCP as it assembles the payload foreach packet from DSP-processed data. A complete packet is then formed bypre-fixing the pre-computed header to its respective payload. Toaccomplish this without moving the payload or the header, a pointercontaining the location of the payload is attached to the header. Whenthe PCP transmits the packet, its indexed DMA controller accesses boththe header and payload from the buffer memory with no intervention bythe PCP itself.

Packetized data is presented by the ATMSAR (item 50 in FIG. 3) over theATMSAR port (item 80 in FIG. 3), with the ATMSAR operating intransparent mode. Normally, the ATMSAR divides the packetized data fromthe PCP into ATM cells, before transmitting it over a network based onthe “Universal Test and Operation Physical Interface for ATM” (UTOPIA)standard. In transparent mode, however, the ATMSAR outputs thepacketized data without modification.

Packet-based or cell-based data may also be received by the voiceprocessor over the ATMSAR port. In this case, the previously describedsequence of events is reversed. Incoming ATM cells are disassembled bythe ATMSAR, with the header information being used to assign payloaddata to TDM channels. After the CRC/Checksum engine verifies cyclicredundancy and checksum values on the incoming data, the PCP moves thedata into the memory of the appropriate DSP and initializes the BMDpointer, flags, etc. to enable fast DMA access of the data by the DSP.Following signal processing operations performed on the data by the DSP,the associated serial ports transmit frame-based TDM data, using theassociated DMA controller to efficiently transfer the data from memory.The same procedure is followed in the case of packet-based data, exceptthat the ATMSAR operates transparently and merely forwards the packetsto the PCP.

In the present embodiment of the voice processor, a telephony signalingcircuit is present in one of the two serial ports associated with eachof the DSPs. This circuit, described in detail below, imposes a verysmall computational burden on the respective DSP and is another novelfeature of the present invention. The telephony signaling componentscorresponding to one DSP are shown in FIG. 5. These components consistof the DSP itself 160, two storage registers 162 and 166, a comparator164 and data selector/transmitter 168. Note that, except for the DSP,all of these components can be created using a small number of standardlogic elements, such as flip-flops and gates.

As explained earlier, the “robbed bit” technique for telephony signalinginserts signal bits in 2 frames of a superframe, or 4 frames of anextended superframe of TDM data, by overwriting (the least significantbit of) voice data in those frames. The telephony signaling bitsindicate line status and typically change very relatively infrequently.Nevertheless, it is important to monitor the state of these bits fromone frame (or superframe) to the next. It would be inefficient torequire the DSP to regularly test the signaling bits, since this woulddivert it from its critical signal processing activities. Instead, thecircuitry shown in FIG. 5 performs this function, and involves the DSPonly when necessary. Incoming TDM data is received by storage register162, which saves the current and previous states of the ABCD signal bitsfor up to 32 channels. The comparator 164 compares the current andprevious signal bit states and interrupts the DSP 160 only when therehas been a change. Since a change in the signal bit state represents achange in the status of the line, the DSP may then take some action inresponse. For example, if the signal bits indicate an “on-hook”condition (meaning that the call has terminated), the DSP would ceaseprocessing data for that channel. Advantageously, the DSP is notdiverted from its other activities unless there is actually a change inthe line status.

The DSP can also control the state of the telephony signaling bits inoutgoing voice data by writing the bit values for a prescribed channelto storage register 166. This need only be done once. Afterwards, thedata selector/transmitter 168 will automatically insert the bit patterninto the voice data for the specified channel in all subsequent frames,until otherwise directed by the DSP. In an alternate mode of operation,telephony signaling is managed by the PCP, rather than the individualDSPs. In this mode, the PCP receives notification from the comparisonregisters of changes in the line status, and also signals line statuschanges using the modification registers.

It will be appreciated by those skilled in the art having the benefit ofthis disclosure that this invention is believed to present a system andmethod for saving and restoring the state of a diagnostic module.Further modifications and alternative embodiments of various aspects ofthe invention will be apparent to those skilled in the art in view ofthis description. Details described herein, such as the number of DSPs,serial ports, etc., are exemplary of a particular embodiment. It isintended that the following claims be interpreted to embrace all suchmodifications and changes and, accordingly, the specification anddrawings are to be regarded in an illustrative rather than a restrictivesense.

1. A time-slot interchange circuit comprising: a plurality of inputports receiving a plurality of input data streams, each of said inputdata streams comprising a plurality of bits; a plurality of shiftregisters, (i) each one of said shift registers having m stages and m isat least two, (ii) each one of said shift registers corresponds to oneof said input data streams and (iii) said bits within each one of saidinput data streams received from said input ports are (a) synchronouslyclocked through said corresponding shift registers in a first mode and(b) asynchronously clocked in a second mode; and a plurality ofmultiplexers routing said bits from said shift registers to a pluralityof output ports, each of said multiplexers temporally selecting saidbits from at least two of said shift registers into a respective one ofsaid output data streams.
 2. The time-slot interchange circuit asrecited in claim 1, wherein (i) said input data streams comprisetime-division multiplexed (TDM) data streams and (ii) at least one ofsaid TDM data streams conveys TDM voice data occupying a plurality oftime-slots in a frame of data.
 3. The time-slot interchange circuit asrecited in claim 1, wherein in said first mode (i) said multiplexersshare a common clock and (ii) said output data streams share frame-synctiming.
 4. The time-slot interchange circuit as recited in claim 1,wherein m=2.
 5. The time-slot interchange circuit as recited in claim 1,wherein each of said input data streams is transferred directly from arespective output node of said input ports to a respective input node ofsaid shift registers.
 6. The time-slot interchange circuit as recited inclaim 1, wherein each of said input data streams is transferred directlyfrom a respective output node of said shift registers to a correspondinginput node of all of said multiplexers.
 7. The time-slot interchangecircuit as recited in claim 1, wherein each of said output data streamsis transferred directly from a respective output node of saidmultiplexers to a respective input node of said output ports.
 8. Thetime-slot interchange circuit as recited in claim 1, wherein aparticular one of said input data streams is clocked into a respectiveone of said shift registers sequentially, one bit at a time.
 9. Thetime-slot interchange circuit as recited in claim 1, wherein saidsynchronous clocking of said shift registers in said first mode iscontrolled through a single one of said input ports.
 10. A method forredistributing a plurality of bits arriving in a plurality of input datastreams to a plurality of output data streams, comprising the steps of:(A) receiving said input data streams at a plurality of input ports; (B)synchronously clocking said bits in each one of said input data streamsreceived from said input ports through a corresponding one of aplurality of shift registers in a first mode, each of said shiftregisters having m stages and m is at least two; (C) asynchronouslyclocking said bits through said shift registers in a second mode; and(D) routing said bits from said shift registers through a plurality ofmultiplexers to a plurality of output ports, each one of saidmultiplexers temporally selecting said bits from at least two of saidshift registers into a respective one of said output data streams. 11.The method as recited in claim 10, wherein (i) said input data streamscomprises a time-division multiplexed (TDM) data streams and (ii) atleast one of said TDM data streams conveys TDM voice data occupying aplurality of time slots within a frame of data.
 12. The method asrecited in claim 10, wherein in said first mode (i) said multiplexersshare a common clock and (ii) said output data streams share frame-synctiming.
 13. The method as recited in claim 10, wherein m=2.
 14. Themethod as recited in claim 10, further comprising the step of:transferring each of said input data streams directly from a respectiveoutput node of said input ports to a respective input node of said shiftregisters.
 15. The method as recited in claim 10, further comprising thestep of: transferring each of said input data streams directly from arespective output node of said shift registers to a corresponding inputnode of all of said multiplexers.
 16. The method as recited in claim 10,further comprising the step of: transferring each of said output datastreams directly from a respective output node of said multiplexers to arespective input node of said output ports.
 17. The method as recited inclaim 10, further comprising the step of: clocking a particular one ofsaid input data streams into a respective one of said shift registerssequentially, one bit at a time.
 18. The method as recited in claim 10,further comprising the step of: controlling said synchronous clocking ofsaid shift registers in said first mode through a single one of saidinput ports.